TSMC Lowers Full-Year Semiconductor Growth Forecast, But Advanced Packaging Demand Outstrips Supply

Semiconductor manufacturing leader TSMC held its annual shareholder meeting on June 6, addressing issues including advanced process development, revenue, and capital expenditure. TSMC’s Chairman Mark Liu and President C.C. Wei answered a series of questions. The key points from the industry are summarized as follows:

2023 Capital Expenditure Leaning towards $32 Billion

For TSMC’s Q2 and full-year outlook for this year, the consolidated revenue forecast is between $15.2 and $16 billion, a decrease of 5%-10% from the first quarter. Gross profit margin is expected to range between 52%-54%, and operating profit margin between 39.5%-41.5%. Chairman Mark Liu revealed that this year’s capital expenditure is expected to lean more towards $32 billion.

TSMC’s President C.C. Wei lowered the 2023 growth forecast for the overall semiconductor market (excluding memory), expecting a mid-single digit percentage decrease. The revenue in the wafer manufacturing industry is expected to decrease by a high single digit percentage. At this stage, the overall revenue for 2023 is expected to decrease by a low-to-mid single digit percentage, sliding approximately 1%-6%.

Advanced Process N4P to be Mass Produced this Year

TSMC’s total R&D expenditure for 2022 reached $5.47 billion, which expanded its technical lead and differentiation. The 5-nanometer technology family entered its third year of mass production, contributing 26% to the revenue. The N4 process began mass production in 2022, with plans to introduce the N4P and N4X processes. The N4P process technology R&D is progressing smoothly and is expected to be mass-produced this year. The company’s first high-performance computing (HPC) technology, N4X, will finalize product design for customers this year.

Advanced Packaging Demand Far Exceeds Capacity

Due to the generative AI trend initiated by ChatGPT, the demand for advanced packaging orders for TSMC has increased, forcing an increase in advanced packaging capacity. TSMC also pointed out that the demand for TSMC’s advanced packaging capacity far exceeds the existing capacity, and it is forced to increase production as quickly as possible. Chairman Mark Liu stated that the current investment in R&D focuses on two legs, namely 3D IC (chip stacking) and advanced packaging.

At present, three-quarters of TSMC’s R&D expenditure is used for advanced processes, and one quarter for mature and special processes, with advanced packaging falling under mature and special processes.

(Photo credit: TSMC)


Disruption in 2.5D/3D Packaging: Hybrid Bonding Rising as New Cornerstone

The surge in AIGC and new technologies such IoT, AI, 5G, AR/VR are driving a huge demand for computational power of high-end chips. This has been even outpacing the performance increase offered by the long-standing Moore’s Law, ushering in a “post-Moore” era where revolutions in advanced chip design are crucial.

Over recent years, chiplet design has seemingly become the mainstream approach for upgrading high-end chips. The concept is to allow more transistors on a single chip, effectively increasing the production yield of high-end chips while reducing overall costs.

By the large, major IC players have all jumped on board. Even Apple has joined the game by releasing their M1 Ultra SoC using the chiplet concept, which doubles computational performance by integrating two M1 Max units in a single chip.

The CPU sector is definitely a clear demonstration of this trend:

  • AMD took the leap with chiplet design in their 2nd-gen EPYC CPUs, doubling the computing cores from 32 to 64 within two years, while slashing costs by up to half. The company has extended this approach to their 4th-gen EPYC CPUs and even pioneered the GPU Navi 31, the first of its kind to use chiplets.
  • Intel started incorporating chiplets into their Lakefield series SoC in 2020. Looking ahead, their upcoming CPUs like the Meteor Lake set for 2023, and Arrow Lake and Lunar Lake scheduled for 2024, will all use chiplet design.

Transition from Bumping to Hybrid Bonding

Our analysis in “Chiplet Design: A Real Game-Changer for Substrates” laid out the comprehensive impact of the evolution of chiplet technology on substrates. In fact, chiplets have already caused a significant disruption to the most advanced semiconductor packaging technologies, necessitating the transition towards advanced 2.5D and 3D packaging technologies.

The bottleneck of advanced packaging lies in the chiplets’ interconnections, with bump and microbump still being the key technology for linking chips and forming I/O joints. These connection densities are hard to enhance, thus limiting the overall chip’s transmission speed. In addition, the more chiplets being stacked, the bigger the chip volume gets. The challenge is how to limit the chip size within a specific range, considering the current technical constraints.

Therefore, copper-to-copper hybrid bonding, also known as DBI (Direct Bond Interconnect), has been emerging as the key technology route that overcomes major hurdles in chiplet integration from the bottom-up.

Unlike bumping technology, hybrid bonding significantly shrinks the I/O joint space. The future transmission demand requires the I/O joint space between chiplets to be less than 10µm. While bumping is limited to around 20µm, hybrid bonding can take this down to an impressive 1µm or even less. This also means more I/O joints can be fitted in the same chip size – even reaching up to millions on a mere 1cm2 chip.

On top of this, hybrid bonding only adds an extra 1-2µm of thickness, compared to the 10-30µm of microbump, thereby helping reduce the thickness of stacked chips.

To put it simply, hybrid bonding can boost transmission efficiency, minimize energy usage with higher density of copper joints, manage chip volume, and even cut down on material costs.

The Race for Advanced Packaging Is Kicking Off

Moving forward, hybrid bonding is set to become the key technology supporting the continuous development of chiplet design and 3D packaging. This has been exemplified by TSMC’s front-end So IC packaging technology which is based on hybrid bonding. This puts AMD, a key customer of TSMC, in a favorable position to get ahead.

From AMD’s roadmap of 3D V-Cache technology, they have stacked SRAM on top of CCX (CPU Complex), and gradually integrated it into Milan-X series, the EPYC server CPUs, and Ryzen series, the consumer-grade CPUs, over the past two years. This has significantly improved performance and power consumption as a whole.

Not to be outdone, this year Intel also launched their Foveros Direct packaging technology, which is also based on hybrid bonding route. Assuming everything proceeds smoothly, we can anticipate the release of CPUs utilizing Foveros Direct technology by 2024.

As we look at the current products, AMD’s hybrid bonding apparently focuses on stacking SRAM and computing units at the moment. However, as CPU leaders deepen their understanding of this technology, the application field is expected to further expand. In other words, the future of hybrid bonding solutions stacking multiple computation units is just around the corner.


Apple Vision Pro Estimated to Ship 200,000 Units in 2024, Concerns around Price and Battery Life Linger, Says TrendForce

TrendForce reports that the recently unveiled Apple Vision Pro at this year’s WWDC is poised to revolutionize the AR/VR market with its sleek design and high-performance capabilities. However, the complexity behind its production and its limited production capacity present significant challenges, leading to a projected initial release in the US during 1H24. Furthermore, considering factors such as pricing and the absence of certain essential features, TrendForce anticipates a modest shipment volume of approximately 200,000 units for Apple Vision Pro in 2024. The market’s response will heavily depend on the subsequent introduction of consumer-oriented Apple Vision models and the ability of Apple to offer enticing everyday functionalities that will drive the rapid growth of the AR market as a whole.

TrendForce also notes that the Apple Vision Pro boasts cutting-edge hardware specifications and innovative design. However, a substantial price tag of US$3,499 and the requirement for an external power source to operate for a mere two hours pose challenges to consumer adoption. Currently, the Apple Vision Pro lacks sufficient applications for mainstream users, making it more attractive to developers and enterprise customers who can capitalize on its innovative features to create diverse applications. Consequently, the higher price point of the product is justified.

Looking ahead, Apple has the opportunity to fine-tune the product specifications based on the usage patterns of various features in Vision Pro. This will pave the way for the launch of a distinct offering, Apple Vision, which will cater to the budgetary constraints of general consumers while optimizing battery life. As such, WWDC 2023 primarily focuses on the concept of spatial computing, setting the stage for the anticipation of more practical AR applications to be showcased at WWDC 2024. These applications will be tailored towards usage in daily life, including seamless integration with other Apple products for information retrieval and effortless command execution.

Will AIGC Bring New Development Boost to MR?

According to TrendForce, it is difficult to see AIGC exerting influence in the MR field in the short term due to the need for corresponding AI models and tools to be established. Currently, the AR/VR market is not large, and coupled with the complexity of content development, it is challenging to attract AIGC’s development in this area in the short term.

Furthermore, the complexity and cost of entry into the MR field, along with limited market size, have caused many brand manufacturers to focus on small-scale commercial products. This is because such products have a high unit price and low quantity, allowing manufacturers to control the total cost within a manageable range while capitalizing on the AR/VR industry trend. However, it does not mean that manufacturers are willing to heavily invest in this market.

Overall, this is the biggest difference in strategy between Apple and these manufacturers. Apple indeed wants to aggressively develop the AR market, but the lack of market understanding and content applications led to the introduction of developer products like Vision Pro. The purpose is twofold: to allow developers to advance in content application development and to gather feedback on hardware design and features used by developers. This feedback helps Apple determine which hardware design and features to retain or discard when launching new consumer products that closely align with content application needs.


TV Panel Demand Slows After E-commerce Festival, June Price Increases Converge

TV panel prices have been on a continuous rise from the bottom of the first quarter to the second quarter, surpassing cash costs. Panel manufacturers are determined to reverse their losses and maintain a strong stance on price hikes. They are also adjusting production rates to maintain the supply-demand balance. However, the demand side indicates a slowdown as the Chinese e-commerce sale season has completed its stocking, and a significant surge in demand is expected to occur in the third quarter. As a result, the overall demand momentum is currently leveling off. Consequently, this month’s price increases for TV panels are expected to show a slight convergence.

Some panel manufacturers are actively increasing monitor panel prices after a period of stability. The prices of Open Cell panel products were previously too low, allowing room for further price increases. This month, prices are expected to rise by USD 0.2~0.5. However, the trend for panel module products is less clear due to varying attitudes toward price hikes among manufacturers, especially newer entrants trying to secure orders with lower prices. As a result, mainstream panel sizes like 23.8 inches and 27 inches are expected to remain mostly unchanged in price this month.

Notebook panel prices have remained stable despite a pricing struggle between brand customers and manufacturers. Demand is steadily increasing, leading panel manufacturers to consider price hikes. However, brand customers are hesitant due to uncertain prospects in the coming months. While there is growth in demand, it is mainly driven by inventory restocking rather than additional demand. As a result, panel prices are expected to stay flat this month, with little room for increases until the end of Q2.


Can MediaTek and NVIDIA Collaborate on Smartphone Chips?

Recently, there has been news of collaboration between NVIDIA and MediaTek. Speculation suggests that the future collaboration may extend to smartphone SoCs, allowing MediaTek to enhance the graphical computing and AI performance of Dimensity smartphone SoCs through NVIDIA’s GPU technology licensing.

Currently, the focus of this collaboration is primarily on NB SoC development, with some progress in the automotive-related chip sector. As for the scope of smartphone SoC collaboration, it is still under discussion, but the potential for related partnerships is worth noting.

In the announced collaboration between NVIDIA and MediaTek for the NB SoC products, MediaTek is mainly responsible for CPU, while other part such as GPU, DSP, ISP, and interface IP are provided by NVIDIA or external partners. NVIDIA holds the leadership position, while MediaTek plays a supporting role in this collaboration.

Regarding the industry’s speculation about possible collaboration in smartphone SoC development, it is estimated that MediaTek will take the lead in the design. Therefore, it is necessary to explore the motivations behind MediaTek’s adoption of related technologies.

Firstly, since the era of the Arm V9 instruction set, Arm’s reference GPU, Immortalis, has incorporated ray tracing functionality, assisting MediaTek’s flagship SoCs in improving gaming performance. This indicates that optimizing gaming scenarios is a key development focus for SoC manufacturers.

However, for high-end gaming applications, the current GPU performance of smartphone SoCs still cannot maintain high frame rates and native resolutions during gameplay. While selecting a pure core stacking approach to improve computational power is effective, it puts pressure on device power consumption. In light of this, Qualcomm introduced Snapdragon Game Super Resolution (GSR) technology this year, which simultaneously reduces power consumption and enhances game graphics quality. MediaTek has not yet explored this technology, and Arm Immortalis has not been released. Therefore, when it comes to GPU performance computing, MediaTek has incentives to seek external collaborations.

Furthermore, with the rapid upgrading of GPUs on smartphone SoCs, PC-level games are now being introduced to smartphones, and industry players are promoting compatibility with graphics APIs, opening doors for NVIDIA, AMD, and even Intel to enter the mobile gaming market. Samsung has partnered with AMD for its Exynos SoC GPU, while NVIDIA, with similar technology to Qualcomm Snapdragon GSR, becomes a logical choice as a cooperation partner for MediaTek.

TrendForce believes that if MediaTek integrates NVIDIA GPUs into Dimensity SoCs and leverages TSMC’s process power efficiency advantages, it could bring a new wave of excitement to MediaTek in the flagship or gaming device market, attracting consumer interest. However, despite the potential technical benefits of collaboration, considering the influence of geopolitical factors, MediaTek, which primarily sells its smartphone SoCs to Chinese customers, may ultimately abandon this collaboration option due to related policy risks.

  • Page 1
  • 68 page(s)
  • 338 result(s)