Although current semiconductor process technologies have evolved to the 3nm and 5nm nodes, SoC (system on a chip) architecture has yet to be manufactured at these nodes, as memory and RF front-end chiplets are yet to reach sufficient advancements in transistor gate length and data transmission performance. Fortunately, EDA companies are now attempting to leverage heterogeneous integration packaging technologies to link the upstream and downstream semiconductor supply chains as well as various IP cores. Thanks to this effort, advanced packaging technologies, including 2.5D/3D IC and SiP, will likely continue to push the limits of Moore’s Law.
While SoC development has encountered bottlenecks, EDA tools are the key to heterogeneous integration packaging
As semiconductor process technologies continue to evolve, the gate length of transistors have also progressed from μm (micrometer) nodes to nm (nanometer) nodes. However, the more advanced process technologies are not suited for manufacturing all semiconductor components, meaning the development of SoC architectures has been limited as a result. For instance, due to physical limitations, memory products such as DRAM and SRAM are mostly manufactured at the 16nm node at the moment. In addition, RF front-end chiplets, such as modems, PA (power amplifiers), and LNA (low noise amplifiers) are also primarily manufactured at the 16nm node or other μm nodes in consideration of their required stability with respect to signal reception/transmission.
On the whole, the aforementioned memory, and other semiconductor components cannot be easily manufactured with the same process technologies as those used for high-end processors (which are manufactured at the 5nm and 3nm nodes, among others). Hence, as the current crop of SoCs is not yet manufactured with advanced processes, EDA companies including Cadence, Synopsys, and Siemens (formerly Mentor) have released their own heterogeneous integration packaging technologies, such as 2.5D/3D IC and SiP (system in package), in order to address the demand for high-end AI, SoC architecture, HPC (high performance computing), and optical communication applications.
EDA companies drive forward heterogeneous integration packaging as core packaging architecture and integrate upstream/downstream supply chain
Although the current crop of high-end semiconductor process technologies is still incapable of integrating such components as memory, RF front-end, and processors through an SoC architecture, as EDA companies continue to adopt heterogeneous integration packaging technology, advanced packaging technologies, including 2.5D/3D IC and SiP, will likely extend the developmental limitations of Moore’s Law.
Information presented during Semicon Taiwan 2021 shows that EDA companies are basing their heterogeneous integration strategies mainly on the connection between upstream and downstream parts of the semiconductor supply chain, in addition to meeting their goals through chip packaging architectures. At the moment, significant breakthroughs in packaging technology design and architecture remain unfeasible through architectural improvements exclusively. Instead, companies must integrate their upstream chip design and power output with downstream substrate signal transmission and heat dissipation, as well as other factors such as system software and use case planning. Only by integrating the above factors and performing the necessary data analysis can EDA companies gradually evolve towards an optimal packaging architecture and in turn bridge the gap of SoC architectures.
With regards to automobiles (including ICE vehicles and EVs), their autonomous driving systems, electronic systems, and infotainment systems require numerous and diverse semiconductor key components that range from high-end computing chips to mid-range and entry-level MCUs. As such, automotive chip design companies must carefully evaluate their entire supply chain in designing automotive chip packages, from upstream manufacturers to downstream suppliers of substrates and system software, while also keeping a holistic perspective of various use cases. Only by taking these factors into account will chip design companies be able to respond the demands of the market with the appropriate package architectures．
As UMC and GlobalFoundries successively end their respective developments of advanced processes, the advanced process market has now become an oligopoly, with TSMC and Samsung as the only remaining suppliers （excluding SMIC, which is currently affected by geopolitical tensions between China and the US）. According to TrendForce’s latest investigations, TSMC holds a 70% market share in advanced processes below – and including – the 1Xnm node, while Samsung’s market share is about 30%.
As electronic products demand faster data transmission speeds and better performance in response to IoT and 5G applications, the chips contained in these products also need to shrink in size and consume less power. Hence, process technologies need to evolve in order to enable the production of increasingly advanced chips. In this light, suppliers of such chips as smartphone AP, CPU, and GPU primarily rely on Taiwan for its semiconductor industry’s advanced process technologies.
Why is Taiwan able to hold key manufacturing competencies, market shares, and unsurpassed technologies in the global foundry industry?
After TSMC pioneered its pure-play foundry services more than 30 years ago, UMC also subsequently transitioned to a foundry business model. However, the build-out and maintenance of wafer fabs require enormous human resources, capital expenditures, and environmental support, all of which have been skyrocketing since the industry progressed below the 40nm node into the EUV era. Factors including governmental support, human resource development, utility services, and long-term amortization and depreciation are all indispensable for foundries to keep up their fab operations. TrendForce’s findings indicate that Taiwan possesses about 50% of the global foundry capacity, and this figure will likely continue growing due to the persistent demand for advanced processes.
Taiwanese foundries led by TSMC and UMC operate based on a pure-play foundry model, which means they do not compete with their clients outside of foundry operations. Foundries are able to maximize the profitability of the semiconductor ecosystem in Taiwan thanks to Taiwan’s comprehensive PC, ICT, and consumer electronics industries.
In addition, not only are they able to deliver PPA（performance, power, and area） advantages to their clients through technology scaling and node shrinking, they are also unsurpassed in their comprehensive silicon IP cores and longstanding product development services. Other competing foundries are unlikely to make breakthroughs in these fields and catch up to Taiwanese foundries in the short run.
On the whole, the Taiwanese foundry industry is able to maintain its leadership thanks to competencies in human capital, client strategies, process technologies, capital intensify, economies of scale, and superior production capacities.
Furthermore, not only do advancements in semiconductor fabrication technology require developmental efforts from foundries, but they also need support throughout the entire supply chain, including upstream wafer suppliers and downstream client feedbacks, both of which can serve to eliminate yield detractors and raise yield rates. Therefore, the Taiwanese semiconductor industry derives its advantage from foundries（TSMC, UMC, PSMC, and VIS）, as well as from the cross-industrial support across silicon wafer suppliers（SAS and GlobalWafers）, fabless IC design clients, and packaging and testing operators（ASE, etc.）